Improvements in semiconductor processing technology have resulted in integrated circuit chips which are more densely populated with microelectronic elements and which provide more functionality than ever before. Furthermore, the aggressive development of semiconductor technology and the accompanying need for higher device integration has enabled current state-of-the-art chips to integrate entire systems on a single small semiconductor die. The need to provide all the possible interconnections to these feature laden chips remains a challenge in the packaging industry, as all the required pads compete for the small peripheral space around the die. The interconnection issue has become even more challenging as these chips are utilizing newer technology nodes to achieve smaller die sizes that are pad limited.
It is conventional to test semiconductor integrated circuits during manufacture to ensure the integrity of the integrated circuits. In one testing technique integrated circuits or dies are tested by establishing electrical current between test equipment such as a tester and each integrated circuit or die. The ability to test the dies in an efficient manner is constantly being reviewed for improvements. It is desirable to be able to increase the throughput of the testing as the die size is shrinking and the pad density is increasing, both of which tend to cause constraints for the testing throughput.
It is within this context that the embodiments described below arise.